Semiconductor memory and method of controlling data therefrom

ABSTRACT

A semiconductor memory, such as a multibit DRAM, has a multiple cell array banks, each having multiple cell arrays. Rows of sense amplifiers are located near each of the cell arrays and extend in a first direction. Multiple rows of transfer switches, also extending in the first direction, are located adjacent to each of the cell array banks. A first data bus, which extends in a second direction which is perpendicular to the first direction, connects the sense amplifiers with the transfer switches. Multiple data buffer rows extend in the first direction near the transfer switches. A second data bus, extending in the first direction, connects the transfer switches with the data buffers. A layout pitch is defined by a spacing between adjacent lines of the first data bus. The transfer switches are placed in accordance with the defined layout pitch and the data buffers are placed according to a layout pitch determined by multiplying the defined layout pitch by the number of cell array banks.

BACKGROUND OF THE INVENTION

The invention relates to a semiconductor memory, and more particularly,to a multi-bit data DRAM cell array.

Referring to FIG. 1, a conventional dynamic random access memory (DRAM)100 employs a hierarchical data bus (GDB, MDB) structure. The DRAM 100comprises a plurality of column decoders 1, a plurality of cell arrays2, and a plurality of column select lines CL extending from the columndecoders 1 over the cell arrays 2. Each column decoder 1 is connected toa corresponding cell column select line CL. Each cell array 2 includes aplurality of memory cells, not shown. The cell arrays 2 are connected tosense-amp rows 3 each of which includes a plurality of sense-amps 4. Thesense-amp rows 3 are connected to data buffers 5 via data buses GDBwhich extend parallel to the column select lines CL. The data buffers 5are in turn connected to a main data bus MDB which extends in adirection orthogonal to the data buses GDB.

When a memory cell is selected by the column select line CL, acorresponding sense-amp 4 in the sense-amp row 3 amplifies data from theselected memory cell and provides it to the data bus GDB. Data on thedata bus GDB is fed to the main data bus MDB via the data buffer 5.

A sense-amp pitch P or its layout pitch is defined in terms of thebreadth occupied by a pair of adjacent sense-amps 4. In this instance,the layout pitch P is substantially equal to a spacing between twoadjacent column select lines CL. On the other hand, the column decoder 1has a breadth equal to the layout pitch P. When the column decoders 1comprise a simple circuit with a reduced number of elements, it ispossible to locate or place the column decoders 1 well within theconstraint of the layout pitch P.

When it is desired to deliver multi-bit data to a peripheral circuitrapidly, the column decoders 1 are replaced by data buffers 5, as shownfor the DRAM 110 in FIG. 2. Also, the column select lines CL arereplaced by data buses GDB extending over the cell arrays-2. The numberof sense-amps 4 connected to each data bus GDB is generally either twoor four for each row 3 (two being shown in FIG. 2). The layout pitch Pis defined by a spacing between two adjacent data buses GDB which issubstantially equal to the breadth occupied by a pair of adjacentsense-amps 4. In this instance, it is necessary that the breadth foreach data buffer 5 be defined by the layout pitch P.

However, it is noted that the data buffer 5 represents a differentialamplifier circuit designed to detect and amplify a minimal potential.Because of the increased complexity of the circuit design for the databuffer 5 in comparison to the column decoder 1 shown in FIG. 1, it isdifficult to establish the breadth of the data buffer 5 according to thelayout pitch P. If an attempt is made to force the breadth of the databuffer 5 into conformity with the defined layout pitch P, a symmetry inthe circuit of the data buffer 5 is lost, leading to inaccuracy of datadetection. One solution would be to increase the number of sense-amps 4connected to a single data buffer 5, thus effectively increasing thelayout pitch P. However, an increased number of sense-amps 4 connectedto each data buffer 5 results in an increase in the load on the databuffer 5, which is undesirable.

It is an object of the invention to provide a semiconductor memory and amethod of controlling data therefrom which facilitate the layout of databuffers.

SUMMARY OF THE INVENTION

To achieve the above objective, the present invention provides asemiconductor memory comprising: a plurality of cell arrays eachincluding a plurality of memory cells; a plurality of data busesconnected to the memory cells disposed in an area of the plurality ofcell arrays; a plurality of transfer switches connected to the pluralityof data buses; and a plurality of data buffers connected in common tothe plurality of transfer switches, wherein the plurality of transferswitches are controlled so that when a specific one of the cell arraysis activated, the plurality of data buses in the specific one of thecell arrays are connected with the plurality of data buffers.

The present invention further provides a method of controlling asemiconductor memory including a plurality of cell arrays each includinga plurality of memory cells, a plurality of data buses connected to thememory cells disposed in an area of the plurality of cell arrays, aplurality of transfer switches connected to the plurality of data buses,and a plurality of data buffers connected in common to the plurality oftransfer switches, the method comprising the steps of: activating aspecific one of the cell arrays; deactivating the remaining cell arrays;turning on the transfer switches associated with the activated the cellarray to connect the plurality of data buses with the plurality of databuffers; and turning off the plurality of transfer switches whichcorrespond to the remaining cell arrays to disconnect the plurality ofdata buses from the plurality of data buffers.

The present invention provides a semiconductor memory, comprising: aplurality of cell arrays, each including a plurality of memory cells; aplurality of sense amplifier rows extending in a first direction in anarea of the plurality of cell arrays, each of the sense amplifier rowsincluding a plurality of sense amplifiers; a plurality of transferswitch rows extending in the first direction adjacent to each of thecell arrays, each of the plurality of transfer switch rows including aplurality of transfer switches; a plurality of first data bus linesconnecting the sense amplifiers with the transfer switches, wherein thefirst data bus lines extend in a second direction which is substantiallyperpendicular to the first direction, each data bus line connecting onesense amplifier in each sense amplifier row to one of the transferswitches; a plurality of data buffer rows extending in the firstdirection, each data buffer row including a plurality of data buffers;and a plurality of second data bus lines extending in the firstdirection and connecting the plurality of transfer switches with thedata buffers.

The present invention further provides a semiconductor memorycomprising: a first and a second memory block, each including memorycells; a first group of data buses for transmitting a data from thememory cells in the first memory block; a second group of data buses fortransmitting a data from the memory cells in the second memory block; afirst group of transfer switches, each connected to corresponding one ofthe first group of data buses; a second group of transfer switches, eachconnected to corresponding one of the second group of data buses; aplurality of data buffers, each coupled to both of corresponding one ofthe first group of transfer switches and one of the second group oftransfer switches; wherein the first and second groups of transferswitches, which receive a control signal, are controlled such that whenone of the first and second groups of transfer switches turns on,another of the first and second groups of transfer switches turns off,in response to the control signal.

Other aspects and advantages of the invention will become apparent fromthe following description, taken in conjunction with the accompanyingdrawings, illustrating by way of example the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with objects and advantages thereof, may best beunderstood by reference to the following description of the presentlypreferred embodiments together with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a cell array structure of aconventional DRAM;

FIG. 2 is a schematic diagram of a cell array structure of aconventional multi-bit output type DRAM;

FIG. 3 is a schematic diagram of a cell array structure of a DRAMaccording to one embodiment of the present invention;

FIG. 4 is a circuit diagram of a transfer switch of the DRAM of FIG. 3;and

FIG. 5 is a circuit diagram of a data buffer of the DRAM of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 3 and 4, a high rate multi-bit output type DRAM 200according to one embodiment of the present invention will now bedescribed. As shown in FIG. 3, the DRAM 200 comprises first and secondcell array banks A1, A2, and data buffer rows 8 connected to the cellarray banks A1, A2 via transfer switch rows 7.

Each of the first and second cell array banks Al, A2 includes aplurality of cell arrays 2 which are preferably disposed one aboveanother as viewed in FIG. 3. Each cell array 2 preferably has an equalnumber of cells. Sense-amp rows 3 including a plurality of sense-amps 4are disposed between adjacent cell arrays 2. The first and second cellarray banks A1, A2 form a pair. When one of the cell arrays 2 isactivated, the remaining cell arrays 2 are deactivated.

The transfer switch rows 7 are disposed parallel to the sense-amp rows3. Each transfer switch row 7 includes a plurality of transfer switches6. In the present example, each transfer switch row 7 includes sixteentransfer switches 6. Each row of data buffers 8 includes a plurality ofdata buffers 5. In the present example, each row of data buffers 8includes eight of the data buffers 5. The data buffer rows 8 aredisposed parallel to the transfer switch rows 7.

A plurality of data buses GDB are located within the first and secondcell array banks Al, A2 and extend a direction orthogonal to thesense-amp rows 3. The number of data buses GDB in the first cell arraybank A1 is equal to the number of data buses GDB in the second cellarray bank A2. The data buses GDB connect the sense-amps 4 with thetransfer switches 6.

A plurality of intermediate data buses MGDB are disposed between thetransfer switch rows 7 and the data buffer rows 8 and extend parallelwith the transfer switch rows 7. Each of the intermediate data busesMGDB is connected to corresponding ones of the data buffers 5 and thetransfer switches 7. The number of intermediate data buses MGDB is equalto the number of data buses GDB in the first cell array bank A1 or thenumber of data buses GDB in the second cell array bank A2.

A plurality of main data buses MDB are shown at the bottom of FIG. 3which are parallel with the intermediate data buses MGDB. Each of themain data buses MDB is connected to an associated one of the databuffers 5. The number of main data buses MDB is equal to the number ofdata buses GDB. The main data buses MDB are connected to individual databuffers 5 in the pair of data buffer rows 8.

Although for the convenience of illustration, each data bus GDB is shownby a single line in FIG. 3, it should be understood that it preferablycomprises a pair of buses including data buses GDBX and GDBZ conveyingcomplementary signals. Also, each intermediate data bus MGDB, which isshown by a single line, preferably comprises a bus pair includingintermediate data buses GDBX and GDBZ conveying complementary signals.In contrast, each of the main data buses MDB preferably comprises only asingle line.

The layout pitch P is defined by a spacing between the data buses GDB,or more exactly, by a spacing between adjacent data buses GDBX. Each ofthe data buses GDB is substantially connected with a pair of sense-amps4 in a single sense-amp row 3. It will be appreciated that the layoutpitch P is substantially the same as the breadth of a pair of sense-amps4.

Each of the data buses GDB is connected to a corresponding transferswitch 6. It will be noted that the transfer switches 6 are disposedalong the sense-amp rows 3 at a spacing of the layout pitch P on oneside of the first and second cell array banks Al, A2. Each of thetransfer switches 6 selectively connects one of the intermediate databuses MGDB and one of the data buses GDB.

The left-most transfer switch 6 associated with each of the first andsecond cell array banks A1, A2 is preferably connected to theintermediate data bus MGDB which is disposed closest to the transferswitch rows 7. The remaining transfer switches 6 which are disposed tothe right of the left-most transfer switch 6 are successively connectedto the intermediate data buses MGDB which are sequentially removed fromthe transfer switch rows 7, as shown in FIG. 3. In this manner, atransfer switch 6 in the first cell array bank A1 and the correspondingtransfer switch 6 in the second cell array bank A2 are connected to acommon intermediate data bus MGDB.

Each data buffer 5 amplifies data read onto one of the intermediate databuses MGDB via an associated transfer switch 6, thus delivering theamplified data to one of the main data buses MDB. Because of the drivecapability required, the data buffers 5 are disposed at a pitch which isabout twice the layout pitch P. In other words, the data buffer 5 has abreadth which is twice the breadth of the transfer switch 6.Accordingly, the number of the data buffers 5 in the first cell arraybank A1 is equal to one-half the number of transfer switches 6 therein.Similarly, the number of the data buffers 5 in the second cell arraybank A2 is equal to one-half the number of transfer switches 6 therein.Thus, the total number of the data buffers 5 is equal to the number ofthe transfer switches 6 contained in either the first or the second cellarray bank A1, A2.

The eight data buffers 5 associated with the first cell array bank A1are connected to the eight intermediate data buses MGDB located close tothe transfer switch row 7. Specifically, the left-most data buffer 5 forthe first cell array bank A1 is connected to the intermediate data busMGDB which is located closest to the transfer switch row 7, and the databuffers 5 which are disposed to the right of the left-most data buffer 5are successively connected to the intermediate data buses MGDB which aresequentially further removed from the transfer switch row 7.

On the other hand, the eight data buffers 5 associated with the secondcell array bank A2 are connected to the eight intermediate data busesMGDB which are located further from the transfer switch row 7.Specifically, the right-most data buffer 5 for the second cell arraybank A2 is connected to the intermediate data bus MGDB which is mostremoved from the transfer switch row 7, and the data buffers 5 which aredisposed to the left of the right-most data buffer 5 are successivelyconnected to the intermediate data buses MGDB which are sequentiallycloser to the transfer switch row 7.

Stated differently, the left-most data buffer 5 is connected to the pairof left-most transfer switches 6 for the first and second cell arraybanks Al, A2 via the intermediate data bus MGDB. The second left-mostdata buffer 5 associated with the first cell array bank A1 is connectedto the pair of second left-most transfer switches 6 for the first andsecond cell array banks A1, A2 via the intermediate data bus MGDB. Theremaining data buffers 5 are similarly connected to pairs of transferswitches contained in the first and second cell array banks A1, A2through corresponding intermediate data buses MGDB. This means that eachdata buffer 5 is shared by a pair of the transfer switches 6.

Referring now to FIG. 4, the transfer switch 6 will be described. Thetransfer switch 6 comprises first and second transfer gate circuits 11,12 and a precharge drive circuit 15 connected to both of the circuits11, 12. The DRAM 200 additionally comprises a control circuit 30 forgenerating a switch enable signal EN used to turn the transfer switch 6on and off.

The first transfer gate circuit 11 is connected to the data bus GDBX andthe intermediate data bus MGDBX and the second transfer gate circuit 12is connected to the data bus GDBZ and the intermediate data bus MGDBZ.The first transfer gate circuit 11 comprises an N-channel MOS transistorT1 and a P-channel MOS transistor T3. The second transfer gate circuit12 comprises an N-channel MOS transistor T2 and a P-channel MOStransistor T4. Each of the N-channel MOS transistors T1, T2 has a gatewhich receives the switch enable signal EN from the control circuit 30via two series connected inverters 13, 14. Each of the P-channel MOStransistors T3, T4 has a gate which receives an inversion of the switchenable signal EN via the inverter 13.

The precharge drive circuit 15 comprises three P-channel MOS transistorsT5, T6 and T7 and is connected between the data bus GDBX and the databus GDBZ. Each of the transistors T5 to T7 has a gate which receives aprecharge signal PR via two series connected inverters 16, 17. Theprecharge drive circuit 15 precharges the data buses GDBX, GDBZ inresponse to the precharge signal PR.

When the switch enable signal EN assumes its H level, the first andsecond transfer gate circuits 11, 12 are both turned on, providingconnections between the data buses GDBX, GDBZ and the intermediate databuses MGDBX, MGDBZ. In contrast, when the switch enable signal ENassumes its L level, the first and second transfer gate circuits 11, 12are both turned off, interrupting the connection between the data busesGDBX, GDBZ and the intermediate data buses MGDBX, MGDBZ. Morespecifically, the first transfer gate circuit 11 selectively connectsbetween the data bus GDBX and the intermediate data bus MGDBX, andsimilarly the second transfer gate 12 selectively connects between thedata bus GDBZ and the intermediate data bus MGDBZ.

Referring now to FIG. 5, the data buffer 5 will be described. The databuffer 5 is a differential amplifier circuit in which its elements arepreferably disposed in a symmetrical manner, thus permitting highaccuracy differential amplification.

The data buffer 5 comprises a pair of first and second N-channel MOStransistors T11, T12 which form an amplifier. Each of the first andsecond NMOS transistors T11, T12 has a gate connected to theintermediate data bus MGDBX or MGDBZ, respectively. The sources of thefirst and second NMOS transistors T11, T12 are connected together and tothe ground via a current controlling N-channel MOS transistor T10. Thefirst and second NMOS transistors T11, T12 also have drains which areconnected to first and second CMOS inverter circuits 21, 22,respectively. The NMOS transistor T10 has a gate which receives a bufferenable signal BEN.

The first and second CMOS inverter circuits 21, 22 together form a latchcircuit. The first CMOS inverter circuit 21 comprises an N-channel MOStransistor T13 and a P-channel MOS transistor T14, which have theirgates or input terminals connected together and their drains (outputterminals) also connected together. The NMOS transistor T13 has a sourceconnected to the drain of the first NMOS transistor T11 and the PMOStransistor T14 has a source connected to a power supply Vcc.

The second CMOS inverter circuit 22 comprises an N-channel MOStransistor T15 and a P-channel MOS transistor T16, which have theirgates (input terminals) connected together and their drains (outputterminals) also connected together. The drains of the transistors T15,T16 are connected to the gates of the transistors T13, T14 and the gatesof the transistors T15, T16 are connected to the drains of thetransistors T13, T14. The NMOS transistor T15 has a source connected tothe drain of the second NMOS transistor T12 and the PMOS transistor T16has a source connected to the power supply Vcc.

The first CMOS inverter circuit 21 has an output terminal which isconnected via series connected inverters 23, 24 to the gate of aP-channel MOS transistor T17. The second CMOS inverter circuit 22 has anoutput terminal which is connected via an inverter 25 to an N-channelMOS transistor T18. The PMOS transistor T17 and the NMOS transistor T18form an output section. Each of the MOS transistors T17, T18 has a drain(output terminal) which is connected to the main data bus MDB. The PMOStransistor T17 has a source connected to the power supply Vcc and theNMOS transistor T18 has a source connected to the ground.

Accordingly, when the output terminal of the first CMOS inverter circuit21 assumes its H level and the output terminal of the second CMOSinverter circuit 22 assumes its L level, the PMOS transistor T17 isturned off and the NMOS transistor T18 is turned on. Consequently, an Llevel data signal is delivered to the main data bus MDB. In contrast,when the output terminal of the first CMOS inverter circuit 21 assumesits L level and the output terminal of the second CMOS inverter circuit22 assumes its H level, the PMOS transistor T17 is turned on and theNMOS transistor T18 is turned off. As a consequence, an H level datasignal is delivered to the main data bus MDB.

The first NMOS transistor T11 has a drain which is connected to thepower supply Vcc via P-channel MOS transistors T19, T20, which form adriver. The second NMOS transistor T12 has a drain which is connected tothe power supply Vcc via P-channel MOS transistors T21, T22, which forma second driver. A node between the PMOS transistors T19, T20 isconnected to the output terminal of the first CMOS inverter circuit 21.A node between the PMOS transistors T21, T22 is connected to the outputterminal of the second CMOS inverter circuit 22. The gates of the PMOStransistors T19-T22 are together and connected to the gate of the NMOStransistor T10 and receive the buffer enable signal BEN.

When the buffer enable signal BEN assumes its L level, the PMOStransistors T19-T22 are turned on and the NMOS transistor T10 is turnedoff. In response thereto, the data buffer 5 has no driving function.This is because turning off the NMOS transistor T10 also turning off thefirst and second NMOS transistors T11, T12, which functions to providean amplification. Because the PMOS transistors T19-T22 are turned on atthis time, an H level is established at both of the output terminals ofthe first and second CMOS inverter circuits 21, 22. Consequently, theMOS transistors T17, T18 in the output section are both turned off,assuming a high impedance condition.

On the other hand, when the buffer enable signal BEN assumes its Hlevel, the PMOS transistors T19-T22 are turned off and the NMOStransistor T10 is turned on. This allows the data buffer 5 to exerciseits driving function. For example, when an L level data signal isdelivered to the intermediate data bus MGDBX and an H level data signalis delivered to the intermediate data bus MGDBZ, the output terminal ofthe second CMOS inverter circuit 22 falls to its L level and the outputterminal of the first CMOS inverter circuit 21 is maintained at its Hlevel. As a consequence, the PMOS transistor T17 is turned off and theNMOS transistor T18 is turned on, whereby an L level data signal isdelivered to the main data bus MDB. In contrast, when an H level datasignal is delivered to the intermediate data bus MGDBX and an L leveldata signal is delivered to the intermediate data bus MGDBZ, an H leveldata signal is delivered to the main data bus MDB.

Referring back to FIG. 3, the operation of the DRAM 200, in particular,the switching action of the transfer switch 6 will now be described. Thetransfer switches 6 in the first cell array bank A1 receive theidentical switch enable signal EN (FIG. 4), and thus are collectivelyturned on or off. Similarly, the transfer switches 6 in the second cellarray bank A2 receive the identical switch enable signal EN, and thusare collectively turned on or off. However, the switch enable signal ENis controlled such that the transfer switches 6 in the first cell arraybank A1 and the transfer switches 6 in the second cell array bank A2cannot be turned on simultaneously. Specifically, when the transferswitches 6 in the first cell array bank A1 receive the switch enablesignal EN-high, the transfer switches 6 in the second cell array bank A2receive the switch enable signal EN-low. For example, when one of thecell arrays 2 in the first cell array bank A1 is activated, the switchenable signal EN-high is applied to the transfer switches 6 in the firstcell array bank A1. At this time, the switch enable signal EN-low isapplied to the transfer switches 6 in the second cell array bank A2which is deactivated.

When the transfer switches 6 in the cell array bank A1 or A2 which isactivated are turned on, the data bus GDB in the cell array bank A1 orA2 is connected to the associated data buffer 5 via the intermediatedata bus MGDB. At this time, the data bus GDB of the cell array bank A1or A2 which is deactivated is not connected to the intermediate data busMGDB (or data buffer 5) which both of the banks A1, A2 share. This isbecause the pair of transfer switches 6 share the single data buffer 5.Accordingly, when any one of the cell arrays 2 in the first and secondcell array banks A1, A2 is activated, data from that cell array 2 is fedto the main data bus MDB via the data buffer 5.

As described above, by allowing the pair of transfer switches 6 to sharea single data buffer 5, the number of data buffers 5 can be reduced toone-half the number of the transfer switches 6, thereby enabling thebreadth of the data buffer chosen equal to twice the layout pitch P. Inthis manner, if the data buffer 5 contains an increased number ofelements, the symmetry of elements within the data buffer can be securedin a reliable manner.

When the memory capacity of the DRAM 200 increases, and it isconstructed in a higher density, it follows that the layout pitch P willbe reduced. Even in such instance, a breadth of the data buffer 5 whichis twice the layout pitch P is secured, thereby allowing the databuffers 5 positively formed without undue restrictions.

It should be apparent to those skilled in the art that the presentinvention may be embodied in many other specific forms without departingfrom the spirit or scope of the invention. Particularly, it should beunderstood that the invention may be embodied in the following forms:

One data buffer 5 may be shared by more than two (or n) cell arraybanks. In this instance, it is possible to achieve a breadth of the databuffer 5 which is n times the layout pitch P.

The circuit arrangement of the data buffer 5 and the transfer switch 6may be suitably changed.

Instead of or in addition to the DRAM 200, the present invention may beapplied to any other semiconductor memory such as a ROM, a static RAM orthe like.

Therefore, the present examples and embodiments are to be considered asillustrative and not restrictive and the invention is not to be limitedto the details given herein, but may be modified within the scope andequivalence of the appended claims.

What is claimed is:
 1. A semiconductor memory comprising:a plurality ofcell arrays each including a plurality of memory cells; a plurality ofdata buses connected to the memory cells disposed in an area of theplurality of cell arrays; a plurality of transfer switches connected tothe plurality of data buses; and a plurality of data buffers connectedin common to the plurality of transfer switches, wherein the pluralityof transfer switches are controlled so that when a specific one of thecell arrays is activated, the plurality of data buses in the specificone of the cell arrays are connected with the plurality of data buffers.2. The semiconductor memory according to claim 1, wherein the pluralityof transfer switches are connected with the plurality of data buffers inthe same sequential order.
 3. The semiconductor memory according toclaim 2, wherein each cell array includes a plurality of sense-ampsconnected to the plurality of data buses, each data bus being connectedwith two of the sense-amps.
 4. The semiconductor memory according toclaim 1, wherein the plurality of memory cells form a plurality of cellarray banks, the transfer switches are disposed according to a layoutpitch defined by a spacing between adjacent data buses, and the databuffers are disposed according to a pitch which is derived bymultiplying the layout pitch by the number of the cell array banks. 5.The semiconductor memory according to claim 4, wherein the number of thecell array banks is equal to two, and the data buffers are disposed at apitch which is twice the layout pitch.
 6. The semiconductor memoryaccording to claim 4, wherein each data buffer comprises a differentialamplifier.
 7. The semiconductor memory according to claim 6, whereineach data buffer includes a plurality of elements disposed in asubstantially symmetrical manner.
 8. The semiconductor memory accordingto claim 1, further comprising a plurality of intermediate data buseswhich connect the plurality of transfer switches with the plurality ofdata buffers.
 9. The semiconductor memory according to claim 8, whereinone data buffer and one transfer switch are connected to a singleintermediate data bus.
 10. The semiconductor memory according to claim8, further comprising a plurality of main data buses which are connectedwith the plurality of data buffers, respectively.
 11. The semiconductormemory according to claim 1, wherein the number of transfer switches isequal to the number of data buffers.
 12. A method of controlling asemiconductor memory including a plurality of cell arrays each includinga plurality of memory cells, a plurality of data buses connected to thememory cells disposed in an area of the plurality of cell arrays, aplurality of transfer switches connected to the plurality of data buses,and a plurality of data buffers connected in common to the plurality oftransfer switches, the method comprising the steps of:activating aspecific one of the cell arrays; deactivating the remaining cell arrays;turning on the transfer switches associated with the activated the cellarray to connect the plurality of data buses with the plurality of databuffers; and turning off the plurality of transfer switches whichcorrespond to the remaining cell arrays to disconnect the plurality ofdata buses from the plurality of data buffers.
 13. A semiconductormemory, comprising:a plurality of cell arrays, each including aplurality of memory cells; a plurality of sense amplifier rows extendingin a first direction in an area of the plurality of cell arrays, each ofthe sense amplifier rows including a plurality of sense amplifiers; aplurality of transfer switch rows extending in the first directionadjacent to each of the cell arrays, each of the plurality of transferswitch rows including a plurality of transfer switches; a plurality offirst data bus lines connecting the sense amplifiers with the transferswitches, wherein the first data bus lines extend in a second directionwhich is substantially perpendicular to the first direction, each databus line connecting one sense amplifier in each sense amplifier row toone of the transfer switches; a plurality of data buffer rows extendingin the first direction, each data buffer row including a plurality ofdata buffers; and a plurality of second data bus lines extending in thefirst direction and connecting the plurality of transfer switches withthe data buffers.
 14. The memory of claim 13, wherein the plurality ofcell arrays form a plurality of cell array banks, each data buffer isconnected to more than one transfer switch, wherein each of theconnected transfer switches is associated with a different one of theplurality of cell array banks.
 15. The memory of claim 13, wherein alayout pitch is defined by a spacing between adjacent first data buslines and wherein the transfer switches are placed in accordance withthe defined layout pitch and the data buffers are placed according to alayout pitch determined by multiplying the defined layout pitch by thenumber of cell array banks.
 16. The memory of claim 13, wherein eachdata buffer comprises a differential amplifier.
 17. The memory of claim13, wherein each transfer switch includes first and second transfer gatecircuits and a precharge drive circuit connected between an inputterminal of each of the first and second transfer gate circuits.
 18. Thememory of claim 13, further comprising a plurality of third data buslines extending in the first direction and connected to the databuffers.
 19. A semiconductor memory comprising:a first and a secondmemory block, each including memory cells; a first group of data busesfor transmitting a data from the memory cells in the first memory block;a second group of data buses for transmitting a data from the memorycells in the second memory block; a first group of transfer switches,each connected to corresponding one of the first group of data buses; asecond group of transfer switches, each connected to corresponding oneof the second group of data buses; a plurality of data buffers, eachcoupled to both of corresponding one of the first group of transferswitches and one of the second group of transfer switches; wherein thefirst and second groups of transfer switches, which receive a controlsignal, are controlled such that when one of the first and second groupsof transfer switches turns on, another of the first and second groups oftransfer switches turns off, in response to the control signal.
 20. Thesemiconductor memory according to claim 19, wherein the first group ofdata buses is disposed on the first memory block and the second group ofdata buses is disposed on the second memory block, and the plurality ofdata buffers are disposed along one end of the first and second memoryblock.